A memory module, as represented by the SIMM (i.e., Single In-line Memory Module), is widely utilized as a semiconductor memory to be mounted on an engineering workstation (EWS) or a computer. The SIMM is usually given a construction in which a semiconductor chip having a memory LSI such as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory) is packaged into an LSI package such as an SOJ (Small Out-line J-leaded Package) and in which a plurality of semiconductor chips are mounted on one or both sides of a printed circuit board.
For the EWS or a parallel processing computer of recent years, however, there is required a memory (RAM) of large capacity for processing massive data at a high speed. In order to meet this requirement, therefore, a three-dimensional technique has been investigated for the memory module. This is because a system having an LSI package planarly (or two-dimensionally) over a printed circuit board has a larger size in the printed circuit board as the memory capacity grows larger.
As a specific example of a three-dimensional memory module, there is known the structure (as disclosed on pp. 33 to 39 of "Electronic Materials" issued on Sep. 1, 1993 by Kogyo Chosakai) in which several layers of very thin LSI packages such as TSOP (Thin Small Out-line Package) are stacked, with the printed circuit boards on their two side walls and in which the leads of the TSOP are held by the side boards.
According to the three-dimensional memory module of this kind, more LSI packages can be mounted on the printed circuit board of the same area to realize a small-size/large-capacity memory module. Moreover, the wiring length for connecting the packages can be made smaller than that of the case that the LSI packages are planarly mounted on the printed circuit board, to raise a great advantage in the aspect of high speed.
However, the three-dimensional memory module of the conventional structure, in which the very thin LSI packages such as TSOP are stacked, has found it difficult to reduce the size of the module and the heat resistance of the package at the same time.
Specifically, when the LSI packages such as TSOP are stacked, the thickness of the resin between the upper and lower semiconductor chips is doubled to increase the heat resistance of the package. In order to lower this heat resistance, therefore, a suitable gap has to be established between the packages so that the external size of the module in the vertical direction is enlarged.
Effective means for reducing the size of the three-dimensional memory module is to package a plurality of semiconductor chips into one package. With this means, the thickness of the resin between the upper and lower semiconductor chips is thinned to reduce not only the external size of the package in the vertical direction but also the heat resistance of the package.
Merely by packaging a plurality of semiconductor chips simply into one package, however, it is impossible to provide a highly reliable memory module. Specifically, when a plurality of semiconductor chips are packaged into one package, it is anticipated that the temperature difference between the center portion and the peripheral portion of the package may become large to cause a serious heat stress in the package. Hence, it is essential to provide a structure design for dissipating the heat of the central portion of the package quickly to the outside.
When a plurality of semiconductor chips are packaged into one package, their testing, screening and aging methods are serious problems. Specifically for the module in which a plurality of semiconductor modules are packaged into one package, none of the semiconductor chips can be replaced even if it is found defective after the packaging step. In order to improve the manufacture yield of the module, therefore, after the semiconductor chips are mounted on the lead frames and subjected to the wire bonding, it is necessary to perform the testing, screening and aging steps for confirming whether or not all the semiconductor chips are normally operating, immediately before the step of packaging the semiconductor chips. In the lead frames before packaged, however, all the leads are electrically connected through tie bars so that the lead frames cannot be tested, screened and aged as they are.
When a plurality of semiconductor chips are packaged into one package, on the other hand, the yield and throughput of the packaging step raise another problem. It is ordinary that the LSI package such as TSOP is molded by the insert molding method of injecting a resin into the gaps between the lead frames sandwiched between the upper part and the lower part. However, when the lead frames mounted with the semiconductor chips are stacked and packaged altogether, it is necessary to eliminate the difficulty which is encountered when parting the package from the conventional mold composed of the top and bottom forces. Other countermeasures are further required against the reluctant flow of the resin into the gaps between the stacked lead frames and against the voids (or clearances).
In the three-dimensional memory module of the conventional structure, on the other hand, all the semiconductor chips are mounted on the lead frames having the same pin array. However, the connections of the data pins are different for the individual semiconductor chips, the lead frames cannot be simply connected in the vertical direction if they have the same pin array. This makes it necessary to arrange the printed circuit board on both side walls of the stacked LSI packages as in the aforementioned memory module disclosed in the foregoing Publication, so that the reduction in the size of the module is restricted.
Moreover, it is difficult for the three-dimensional memory module having the conventional structure to be adapted to multiple bits. Specifically, a multi-bit device having a large data width such as a memory module of 36 bits has found it difficult to design the lead frames in a small size because of many data lines, so that the package size and the bonding wire length have to be increased. Thus, it has been difficult for the prior art to mount a multi-bit device on a small-sized memory module.
An object of the present invention is to provide a small-size/high-performance multi-chip module and a small-size/large-capacity memory module.
An object of the present invention is to provide a method for manufacturing a small-size/high-performance multi-chip module.
An object of the present invention is to provide an apparatus for manufacturing a small-size/high-performance multi-chip module.
Another object of the present invention is to provide a technique which can provide the small-size/ high-performance multi-chip module at a reasonable cost.
Another object of the present invention is to provide a technique which can reduce the size of the multi-chip module mounted with multi-bit devices.
Another object of the present invention is to provide a technique which can improve the heat radiation properties of the multi-chip module.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.